Design Tools- Models
Design Automation - EDA
Program with integrated Schematic Capture, PCB layout and
Electronic design automation (EDA or ECAD) is a category
of software tools for designing electronic systems such
as printed circuit boards and integrated circuits. The tools
work together in a design flow that chip designers use to
design and analyze entire semiconductor chips
specifically with respect to integrated circuits.
digital flows are extremely modular (see Integrated circuit
design, Design closure, and Design flow (EDA)). The front
ends produce standardized design descriptions that compile
into invocations of "cells,", without regard to
the cell technology. Cells implement logic or other electronic
functions using a particular integrated circuit technology.
Fabricators generally provide libraries of components for
their production processes, with simulation models that
fit standard simulation tools. Analog EDA tools are far
less modular, since many more functions are required, they
interact more strongly, and the components are (in general)
for electronics has rapidly increased in importance with
the continuous scaling of semiconductor technology. Some
users are foundry operators, who operate the semiconductor
fabrication facilities, or "fabs", and design-service
companies who use EDA software to evaluate an incoming design
for manufacturing readiness. EDA tools are also used for
programming design functionality into FPGAs.
High-level synthesis(syn. behavioural synthesis, algorithmic
synthesis) For digital chips
Logic synthesis translation of abstract, logical language
such as Verilog or VHDL into a discrete netlist of logic-gates.
Schematic Capture For standard cell digital, analog, rf
like Capture CIS in Orcad by CADENCE and ISIS in Proteus.
Layout like Layout in Orcad by Cadence, ARES in Proteus.
Transistor simulation ¡V low-level transistor-simulation
of a schematic/layout's behavior, accurate at device-level.
Logic simulation ¡V digital-simulation of an RTL or gate-netlist's
digital (boolean 0/1) behavior, accurate at boolean-level.
Behavioral Simulation ¡V high-level simulation of a design's
architectural operation, accurate at cycle-level or interface-level.
Hardware emulation ¡V Use of special purpose hardware to
emulate the logic of a proposed design. Can sometimes be
plugged into a system in place of a yet-to-be-built chip;
this is called in-circuit emulation.
Technology CAD simulate and analyze the underlying process
technology. Electrical properties of devices are derived
directly from device physics.
Electromagnetic field solvers, or just field solvers, solve
Maxwell's equations directly for cases of interest in IC
and PCB design. They are known for being slower but more
accurate than the layout extraction above.
Clock Domain Crossing Verification (CDC check): Similar
to linting, but these checks/tools specialize in detecting
and reporting potential issues like data loss, meta-stability
due to use of multiple clock domains in the design.
Formal verification, also model checking: Attempts to prove,
by mathematical methods, that the system has certain desired
properties, and that certain undesired effects (such as
deadlock) cannot occur.
Equivalence checking: algorithmic comparison between a chip's
RTL-description and synthesized gate-netlist, to ensure
functional equivalence at the logical level.
Static timing analysis: Analysis of the timing of a circuit
in an input-independent manner, hence finding a worst case
over all possible inputs.
Physical verification, PV: checking if a design is physically
manufacturable, and that the resulting chips will not have
any function-preventing physical defects, and will meet
Mask data preparation, MDP: generation of actual lithography
photomask used to physically manufacture the chip. Resolution
enhancement techniques, RET ¡V methods of increasing of
quality of final photomask.
Optical proximity correction, OPC ¡V up-front compensation
for diffraction and interference effects occurring later
when chip is manufactured using this mask.
Mask generation ¡V generation of flat mask image from hierarchical
Automatic test pattern generation, ATPG ¡V generates pattern-data
to systematically exercise as many logic-gates, and other
components, as possible.
Built-in self-test, or BIST ¡V installs self-contained test-controllers
to automatically test a logic (or memory) structure in the