PCB Layout Performance Guideline For 10/100/1000Mbps Magnetic Connectors

   
 

From Xmultiple Engineering Dept.


Xmultiple provides this printed circuit board layout guide to assist our customers in their board layout designs for their products. The guide will help our customers products comply with both EMI and ESD standards using Xmultiples 10/100Mbps and 1 Gigabit magnetic connector family of Ethernet products. Xmultiple uses the trademark name of UltraMag for our magnetic connectors.

Our customers know the critical issues of printed circuit board (PCB) layout is the single most important factor that affects EMI, ESD and overall performance of their products. In order to meet these requirements depend on good design practices. The goal of the guide is to minimize digital and common mode noise as well as to provide shielding between the PCBs internal circuitry and the external environment. These PCB design practices should apply to the entire PCB design, not only to Xmultiple Ethernet connector products.
All datasheets and support documentation can be found on Xmultiples web site at: www.Xmultiple.com.

PCB Layout General Rules

  • The location of the components/connectors placement on the board should be performed in a best location to avoid long loop traces.
  • A metal box should be used to shield the printed circuit board.
  • Your DC power cord should use a ferrite core to reduce EMI.
  • Industry guidelines should be followed to layout differential pairs, the ground plane, and high-speed signals.
  • Use a power supply which is rated for the application in which your product will be use.
  • Optimized with decoupling capacitors.
  • Keep power and ground noise under 50mV peak to-peak.
  • Provide controlled impedance on all clock lines and high-speed digital signals traces with right termination schemes to prevent reflection and ringing.
  • Switching DC-DC converter is to be filtered and properly shielded as the DC-DC power converter can produce a great deal of EMI noise.
  • We recommend no via and pad in the path on any critical signal. The layout of via and pads will induce unwanted capacitance and inductance which can cause reflection and distortion.

Power Ground Rules

  • Llayout should not split the ground plane into separate planes for analog, digital, power pins. A single and contiguous ground plane is recommended.
  • Route high-speed signals above a solid and unbroken ground plane.
  • Fill copper in the unused area of signal planes and connect these coppers to the ground plane through vias.
  • Stagger the placement of vias to avoid creating long gap in the plane due to via voids.

Analog VCC Plane

Place and route analog components within the Analog

VCC plane.

Place and route components within the VCC plane.

Digital VCC plane

Place and route digital components within the Digital VCC plane.

Signal Ground

The signal ground region should be one continuous and unbroken plane. Both analog (AGND) and digital (DGND) grounds should be directly connected to the signal ground plane.

Chassis Ground

The chassis ground and magnetics serve two purposes: they help to reduce EMI noise emissions from the signal ground plane to the PCBs external environment and also act as a shield to protect the PCB components from ESD. Place the chassis ground on all PCB layers and use connection mounting holes to join the chassis ground on different PCB layers This chassis ground on the PCB is directly connected to the metal shield of equipment through the connection mounting holes. Use a trench/moat to isolate the chassis ground plane from the signal ground plane. The chassis ground region extends from the front edge of the PCB board (RJ45 connectors) to the magnetics and around the edge of the board. Ground Chassis information.

Magnetic Noise Zone

E Void both power and ground planes on all PCB layers directly under the magnetics.
E Chassis ground should extend from the magnetics to the RJ45 connector.
E Do not route any digital signals between the PHY and RJ45 connector.

Differential Signal Layout

E Differential pair (TX+/- or RX+/-) should be routed away from all other signals and close together to use 5-mil trace width and 5-mil trace space in same length as possible with 100 ohms controlled trace.
E Keep both traces of each differential pair as identical to each other as possible.
E Route each differential pair on the same PCB layer.
E Route both TX+/- and RX+/- pairs as far as away from each other at least four times of 5-mil trace space.

PCB Layer Stacking

6-Layer Example:
V Layer 1 component + signal side (short traces)
V Layer 2 ground plane
V Layer 3 signal
V Layer 4 signal
V Layer 5 power plane
V Layer 6 signal

4-Layer Example:
V Layer 1 component + signal side (short traces)
V Layer 2 ground plane
V Layer 3 power plane
V Layer 4 signal

Clock Layout Guidelines

E Keep clock traces as short as possible.
E Ensure that all clock traces should have an unbroken reference ground plane.
E Use a clock driver when driving multiple loads from a single oscillator.
E All clock signals should be terminated. For example, place a 33-50 ohm series resistor close to the clock source.

ESD Protection Considerations

For ESD Protection your layouts most important issue for designing your PCBs with regard to ESD compliance is to consider how the ESD currents will flow to earth and where the ESD voltages will appear, to avoid other circuitry malfunctioning or even being destroyed.
Various ESD protection methods and devices can be used. The level of ESD protection provided by each method varies and depends on the type of protection device used. Consult the specific manufactures data sheet to determine the level of ESD protection and proper connection.

E Place transient voltage suppressor (TVS) devices on the TX +/- and RX+/- differential pairs to help increase ESD protection. These devices are connected in parallel with the I/O lines to be protected.
E In your layout all unused inputs should be connected to either ground with a 1K resistor or power with a 10K resistor, depending on the desired strap-in setting of the chip.
E Place termination resistors for the TX+/- and RX+/- differential pairs close to the Xmultiple magnetic connector.
E During FCC or ESD tests, remove all unused header pins, jumpers, test point pins, etc.
These parts act as antenna and can degrade test results.

Xmultiple has local field application engineers how developed this guide. For additional assistance please contact your local Xmultiple Field Application Engineer or Xmultiple salesperson.


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